1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to improve efficiency and operation speed.
2. Discussion of the Related Art
Generally, in a field-effect transistor (FET) of an existing metal oxide semiconductor (MOS) structure, a region contacted to a transistor driving circuit is made of titanium silicide or cobalt silicide so as to decrease a contact resistance between the transistor and the transistor driving circuit. That is, the cobalt silicide (CoSi2) is formed on a transistor having a gate length of 0.18 μm or less, which substitutes for tungsten silicide (WSi2) and titanium silicide (TiSi2) that have been used for a prior art transistor.
The cobalt silicide (CoSi2) is formed in the following process steps. A silicon substrate is prepared, and impurity ions are injected into the silicon substrate to form source/drain regions. Subsequently, a rapid thermal processing (RTP) process is performed on the silicon substrate so as to activate the impurity ions, and a double layer of cobalt (Co) and titanium (Ti) is deposited on the silicon substrate. A rapid heat treatment process is performed on the silicon substrate in an atmosphere of N2.
The aforementioned cobalt silicide increases a saturation current value, so that device turning on/off characteristic is improved, thereby easily driving the device at a low voltage. Also, the contact resistance decreases between a line and the transistor, thereby improving an operation speed of the device. Accordingly, the silicide process is necessary to form a logic device.
A prior art method for manufacturing a semiconductor device will be explained with reference to the accompanying drawings.
FIG. 1A to FIG. 1E are sectional views illustrating the prior art method for manufacturing the semiconductor device.
As shown in FIG. 1A, an active region and a field region are defined on a semiconductor substrate 11. The field region of the semiconductor substrate 11 is etched at a predetermined depth through photolithography and etching processes, thereby forming a trench. Then, the trench is filled with an insulating material, so that a barrier 12 is formed on the field region of the semiconductor substrate 11. A gate insulating layer 13 is formed on an entire surface of the semiconductor substrate 11 including the barrier 12, and a poly silicon layer 14 as a gate electrode is formed on the gate insulating layer 13. After that, n-type or p-type impurity ions are selectively injected to the poly silicon layer 14, and a predopping anneal process is performed thereon.
Referring to FIG. 1B, the poly silicon layer 14 and the gate insulating layer 13 are selectively removed through photolithography and etching processes, thereby forming the gate electrode 14a. Then, lightly doped drain (LDD) ions are injected to the entire surface of the semiconductor substrate 11 by using the gate electrode 14a as a mask, thereby forming an LDD region 15 at both sides of the gate electrode 14a on the surface of the semiconductor substrate 11. If the semiconductor substrate 11 is in a state of p-type, n-type impurity ions are injected to the semiconductor substrate 11. Meanwhile, if the semiconductor substrate 11 is in a state of n-type, p-type impurity ions are injected to the semiconductor substrate 11.
After forming the insulating layer on the entire surface of the semiconductor substrate 11 including the gate electrode 14a shown in FIG. 1C, an etching back process is performed on the entire surface of the semiconductor substrate, thereby forming sidewall spacers 16 at both sides of the gate electrode 14a. Subsequently, heavily doped n-type impurity ions are injected into the entire surface of the semiconductor substrate 11 by using the gate electrode 14a and the sidewall spacer 15 as the mask, so that source/drain regions 17 are formed on the surface of the semiconductor substrate 11.
As shown in FIG. 1D, a cobalt layer 18 and a titanium layer 19 are sequentially deposited on the entire surface of the semiconductor substrate 11 including the gate electrode 14a. The heat treatment is performed on the semiconductor substrate 11, and a cobalt silicide layer 20 is formed on the surface of the semiconductor substrate 11 including the poly silicon layer 14 and source/drain regions 17. Subsequently, the titanium layer 19 and the cobalt layer 18 are removed by wet-etching process, which are not reactive on the surfaces of the polysilicon layer 14 and the source/drain regions 17.
However, the prior art method for manufacturing the semiconductor device has the following problems.
In the prior art method for manufacturing the semiconductor device, the silicide layer is distant from a channel region, so that a resistant material increases between the silicide layer and the channel region, thereby deteriorating device quality and operation speed.